In the production process of semiconductor integrated circuit devices, after a great number of integrated circuits are formed on a wafer, a probe test is generally conducted as to each of these integrated circuits. This wafer is then cut, thereby forming semiconductor chips. Such semiconductor chips are contained and sealed in respective proper packages. Each of the packaged semiconductor integrated circuit devices is further subjected to a burn-in test. In order to give a quality certification to a semiconductor integrated circuit device, it is extremely important to not only inspect electrical properties of the semiconductor integrated circuit device by the burn-in test, but also inspect electrical properties of the semiconductor chip itself. Besides, in recent years, there has been developed a mounting method that a semiconductor chip itself is used as an integrated circuit device to directly mount a circuit device composed of the semiconductor chip on a printed circuit board. Therefore, there is a demand for guaranteeing the quality of the semiconductor chip itself.
Since the semiconductor chip is minute, and its handling is inconvenient, the inspection of the circuit device composed of the semiconductor chip is complicated, and so it takes a long time to conduct the inspection, and inspection cost thus becomes considerably high.
From such reasons, attention has been recently paid to a WLBI (Wafer Level Burn-in) test in which the electrical properties of a circuit device composed of a semiconductor chip are inspected in the state of a wafer.
On the other hand, in the probe test conducted on integrated circuits formed on a wafer, a method, in which a probe test is collectively performed on, for example, 16 or 32 integrated circuits among a great number of integrated circuits formed on a wafer, and the probe test is successively performed on other integrated circuits, is generally adopted.
In recent years, there has been a demand for collectively performing a probe test on, for example, 64, 124 or all integrated circuits among a great number of integrated circuits formed on a wafer for the purpose of improving inspection efficiency and reducing inspection cost.
FIG. 18 is a cross-sectional view schematically illustrating the construction of an exemplary conventional wafer inspection apparatus for conducting the WLBI test or probe test as to a wafer on which a great number of integrated circuits have been formed. Such wafer inspection apparatus are described in, for example, Prior Art. 1 and Prior Art. 2.
This wafer inspection apparatus has a circuit board 80 for inspection, on the front surface (lower surface in the figure) of which a great number of inspection electrodes 81 have been formed, and a probe card 90 is arranged on the front surface of the circuit board 80 for inspection through a connector 85. This probe card 90 is constructed by a circuit board 91 for connection and a contact member 95 provided on the front surface (lower surface in the figure) of the circuit board 90 for connection and having a great number of contacts (not illustrated) brought into contact with electrodes (not illustrated) to be inspected of integrated circuits in a wafer 1 that is an object of inspection. A wafer tray 96 also serves as a heating plate, on which the wafer 1 that is the object of inspection is mounted, is arranged under the contact member 95. Reference numeral 97 indicates a pressurizing mechanism for pressurizing the circuit board 80 for inspection downward.
On a back surface of the circuit board 91 for connection in the probe card 90, a great number of terminal electrodes 92 are formed in accordance with a pattern corresponding to a pattern of the inspection electrodes 81 of the circuit board 80 for inspection, and the circuit board 91 for connection is arranged in such a manner that the terminal electrodes 92 are respectively opposed to the inspection electrodes 81 of the circuit board 80 for inspection by guide pins 93.
In the connector 85, a great number of connecting pins 86 called “pogo pins”, which can be elastically compressed in a lengthwise direction thereof are arranged in accordance with the pattern corresponding to the pattern of the inspection electrodes 81 of the circuit board 80 for inspection. The connector 85 is arranged in a state that the connecting pins 86 have been respectively located between the inspection electrodes 81 of the circuit board 80 for inspection and the terminal electrodes 92 of the circuit board 91 for connection.
In the wafer inspection apparatus shown in FIG. 18, the wafer 1 that is the object of inspection is mounted on the wafer tray 96, and the circuit board 80 for inspection is pressurized downward by the pressurizing mechanism 97, whereby each of the connecting pins 86 of the connector 85 are elastically compressed in the lengthwise direction. As a result, the inspection electrodes 81 of the circuit board 80 for inspection are electrically connected to their corresponding terminal electrodes 92 of the circuit board 91 for connection, and the respective contacts of the contact member 95 come into contact with electrodes to be inspected of a part of the integrated circuits formed on the wafer 1, thereby achieving necessary electrical connection. The wafer 1 is then heated to a predetermined temperature by the wafer tray 96 to perform necessary electrical inspection (WLBI test or probe test) as to the wafer 1 in this state.
However, the conventional wafer inspection apparatus shown in FIG. 18 involves such problems as described below.
In this wafer inspection apparatus, it is necessary to pressurize the respective connecting pins 86 under pressurizing force of, for example, about 0.8 N (about 0.08 kgf) per pin for the purpose of achieving stable electrical connection of the inspection electrodes 81 of the circuit board 80 for inspection to their corresponding terminal electrodes 92 of the circuit board 91 for connection. Accordingly, for example, when the number of the inspection electrodes 81 of the circuit board 80 for inspection is, for example, 5,000, pressurizing force of about 4,000 N is required as a whole. Therefore, the apparatus involves a problem that the pressurizing mechanism 97 for applying such pressurizing force inevitably becomes large in size, so that the whole wafer inspection apparatus becomes considerably large in size.
The apparatus also involves a problem that the service life of the circuit board 80 for inspection is shortened because each of the inspection electrodes 81 of the circuit board 80 for inspection are pressurized under great pressurizing force by the respective connecting pins 86, whereby the inspection electrodes 81 are liable to be damaged, and in turn, inspection cost is increased.
There is a limit to a reduction in length of the connecting pins 86 from the constraint of mechanism, and the connecting pins are actually required to have a length of about 3 cm. Therefore, a clearance between the circuit board 80 for inspection and the circuit board 91 for connection becomes considerably long. As a result, it is difficult to reduce the size of the wafer inspection apparatus in a height-wise direction. In this respect, the apparatus also involves a problem that the whole wafer inspection apparatus cannot be miniaturized. In particular, there has recently been proposed a wafer inspection apparatus constructed by stacking a plurality of inspection units each composed of the respective components shown in, for example, FIG. 18 for the purpose of performing inspection as to a plurality of wafers in a small operating space in parallel. In such a wafer inspection apparatus, it is extremely important from the viewpoint of miniaturizing the apparatus to reduce the size of each inspection unit in a height-wise direction because the whole wafer inspection apparatus becomes considerably large when the size of each inspection unit in the height-wise direction is large.
Since the connecting pins 86 require to have a considerably long length, a distance of a signal transmission system becomes considerably long, so that a problem that the apparatus is difficult to be adapted to electrical inspection as to high functional integrated circuits of which high-speed processing is required arises.    Prior Art. 1: Japanese Patent Application Laid-Open No. 2000-147036;    Prior Art. 2: Japanese Patent Application Laid-Open No. 2000-323535.